Versatile DRAM Interface for the 6502

  By: Description
Hardware K. Howell 6502, two 64Kx4 DRAM chips, TTL logic.
Software K. Howell  
Article K. Howell Published in Electronics Today International, 1985

This project is a dynamic memory board which plugs into a 6502 socket (40-pins).

At the time of this project (1984), memory was expensive. The home computer boom (pre IBM PC) saw a proliferation of many different computers. The simpler ones used static RAM, which was easy to design with but expensive. 8Kx8 chips were reasonable value, but 32K chips were not. The more advanced ones used DRAM which was much cheaper and denser.

The down side of DRAM is that it is harder to design with than SRAM. There are more complex timings to satisfy. They need regular refreshing, and the address lines need to be multiplexed.

There are various ways to refresh DRAM, most of which are quite complex. Texas Instruments made the TMS4500 DRAM controller (a 40-pin chip in itself) which would make the CPU wait if a refresh cycle was in progress. The Z80 helped by having a 7-bit refresh row counter. Neither of which is very useful to the 6502 which does not support wait states.

The 6502 does have one significant advantage: the memory access cycles are very regular. The 6502 has a single clock output with a 50% duty cycle. If the memory is fast enough, it is possible to use the last half (clock high) for CPU access, and the first half (clock low) for something else.

The 6502 based BBC micro used DRAM (16Kx1bit chips) to give 16 or 32 Kbytes of RAM. It used the method above to interleave CPU and video controller access to memory. Video memory access is a regular stream of incrementing addresses, so this also had the beneficial side effect of performing the refresh!

BBC micros cost around 400 (in 1985), eight times more than my 50 second-hand Acorn Atom. The BBC had much of its logic in several semi-custom ULA chips which were not easily or cheaply available outside Acorn. So I had to think of some other way that used easily and cheaply available TTL logic chips.

First I needed to provide two DRAM cycles in one CPU clock cycle. For a start, I needed two RAS cycles, the first for the refresh row and the second for the CPU row. In a flash of inspiration I realised this could be done by delaying the 1MHz clock by about 200ns and XORing the delayed and the original clocks.

Next I needed a ROW/COLUMN select signal to drive the multiplexers. The DRAM data sheet showed the row hold time was much smaller than the set up time. In fact the address lines could change almost as soon as the RAS falling edge had clocked in the row address. The multiplexers would probably provide enough delay, but just to make sure I used the /RAS signal delayed by a single TTL gate.

The CPU address and refresh row counter multiplexing was done by two LS257 chips on the CPU side, and an LS244 tristate buffer to an LS393 binary counter on the other.

Finally I needed some way to control /CAS so that it was only asserted for the CPU access, and only in certain memory locations. This was easily done by an LS139 decoder. This took in the ROW/COLUMN signal and delayed it by its single TTL gate delay, and routed it to emerge as one of four outputs controlled by A15 and A14.

The 200ns delay was non trivial. The high and low LS TTL logic threshold values are not symmetrical either side of VCC/2, so a resistor and a diode were added to make the discharging curve faster than the charging curve. The Schmitt trigger sensor was probably a significant load on the delay network.

The delay network did not perform as planned, so the two resistors were changed to preset variable resistors which were adjusted for a satisfactory delayed clock.

Once this was done, the design worked as planned. I then designed an ADC board for the Atom expansion bus and wrote a program for the Atom to demonstrate the large capacity of the DRAM as a delay line for digitised ADC values.

As a bonus, the board plugged into the 6502 socket, making it independent of the many expansion buses in use. These were either mutually incompatible or absent altogether.

The versatility of this design is that it can easily be adapted for video-refresh interleaving. The LS393 and LS244 can be replaced by a pair of LS257 chips multiplexing the address lines of a 6845 video controller chip. Some care is required to ensure the most frequently changing video address lines multiplex into the row address, as other lines may not cycle through all rows in the DRAM refresh period.

When using 16Kx4 bit chips, take care that the most significant address lines A14 and A15 multiplex into the row on MA0 and MA7 respectively. The 16Kx4 bit RAM chips use an 8-bit column address but only 6-bits of row address (from MA1-6). This precaution will ensure easy upgrades from two 16Kx4 to two 64Kx4 chips.

The chip count is as follows:

'257 x2 2:1 tristate multiplexers
'244 x1 8-bit tristate buffer
'393 x1 8-bit counter
'86 x1 Quad XOR gates
'132 x1 Quad NAND gates, Schmitt trigger
'139 x1 Dual 1 of 4 decoder

Nowadays (1999), a 32K RAM chip can be had for about 1.50 which is cheaper and simpler if you only want memory. However if you want an interleaved video memory system then you would need at least three '257 chips to multiplex the address lines, and so this DRAM design becomes competitive again.

Either way, it is a very useful circuit for demonstrating and experimenting with DRAM. Perhaps for college students. HCMOS technology (74HC) has more symmetrical logic thresholds, and lower power drain, so you should be able to simplify the RC network as well as the usual benefits of better noise immunity.

Timing

PH2 PH2' RAS MUX CAS Action
VDU
accesses
data here
1 High for 200ns:




/RAS strobes in row
COL 0  
ROW  
1  
0 0 MUX selects column, <25 ns later
COL /CAS strobes in column, <25 ns later
0 > 250ns
from
/CAS falling
to
PH2 rising
(>150ns DRAM acess time
plus 100ns data setup time
CPU
accesses
data here
High for 200ns:




/RAS strobes in row
 
ROW  
1  
1 0 MUX selects column
COL /CAS strobes in column
0 > 250ns
from
/CAS falling
to
PH2 rising
(>150ns DRAM acess time
plus 100ns data setup time
   
a /RAS delayed = /MUX
b d and c exclusive-ored = /RAS
c 1.00 MHz = delayed by 200 ns
d 1.00 MHz = CLK Phase 2